Field of the Invention
The present invention relates to a level shift circuit which interfaces between two logic circuit blocks driven by two voltages. More particularly, the present invention relates to a level shift circuit which interfaces between two logic circuit blocks in which a power management controlling such that on and off of a power source is performed for each circuit block such as single chip ICs, e.g., LSIs.
Discussion of the Related Art
Recently, with miniaturization of LSIs (i.e., with increase of integration degree of LSIs), a number of circuits can be contained in a chip. Power management is performed on such LSIs. Namely, the circuit blocks in such LSIs are connected to respective power sources so that power consumption can be reduced and a proper voltage can be applied to each of the circuit blocks. In addition, a power is supplied to only circuits which need a power supply. Therefore, when signals are exchanged between circuit blocks using different power sources, a level shift circuit is used.
FIG. 3 is a schematic view illustrating a conventional level shift circuit.
Referring to FIG. 3, a level shift circuit 100 performs level shift on a logic signal sent from a first logic circuit 101 to which a first voltage Vdd1 is applied from a power source to output the level-shifted signal to a second logic circuit 102 to which a second voltage Vdd2 greater than the first voltage Vdd1 is applied from a power source.
The level shift circuit 100 is constituted of a switching device SWa including a N-channel MOS transistor; a latch circuit 111; a first control circuit 112 which controls the operation of the switching device SWa depending on the first voltage Vdd1; and a latch control circuit 113 which controls the operation of the latch circuit 111 depending on the first voltage Vdd1.
In the level shift circuit 100, a case in which the first voltage Vdd1 is 1.5 V which is greater than a predetermined voltage a, the second voltage is 3.0 V, and the threshold voltage of the switching device SWa is 0.5 V will be explained below.
When a High level signal of 1.5 V is input to an input terminal SIN of the level shift circuit 100, a High level control signal SaB of 1.5 V is input from the first control circuit 112 to a gate of the switching device SWa, and thereby the switching device SWa is turned on.
When the switching device SWa is turned on, a voltage of 1.0 V, i.e., difference between the first voltage Vdd1 (1.5 V) and the threshold voltage (0.5V) of the switching device SWa, is applied to one of input terminals of a NAND circuit 121 of the latch circuit 111. By making the current driving ability of an output circuit (not shown) of an inverter 122 less than that of an output circuit (not shown) of the first logic circuit 101, the voltage of the input terminal of the NAND circuit 121 can be increased so as to be about 1.0 V.
In this case, by setting the threshold voltage of the NAND circuit 121 so as to be not greater than 1.0 V, the output terminal of the NAND circuit 121 achieves a Low level (i.e., 0 V), and thereby a High level signal of 3.0 V is output to an output terminal OUT by an inverter 123. At the same time, a High level signal of 3.0 V is input to the input terminal of the NAND circuit 121 via the inverter 122.
Although the output circuit of the inverter 122 has a little current driving ability, the inverter 122 works to further increase the source voltage of the switching device SWa so as to be greater than 1.0 V. Since the gate voltage of the switching device SWa is 1.5 V, the switching device SWa achieves an OFF state.
When the switching device SWa achieves an OFF state, the source voltage of the switching device is further increased, and finally the source voltage reaches 3.0 V, which is the same as the output voltage of the inverter 122, and thereby the switching device SWa achieves a perfect OFF state. As a result, it is prevented that a current is flown from the second logic circuit 102, which is operated by the second voltage Vdd2 greater than the first voltage Vdd1, to the first logic circuit 101, which is operated by the first voltage Vdd1 smaller than the second voltage Vdd2.
When a Low level signal (i.e., 0 V) is input to the input terminal SIN, a High Level control signal SaB of 1.5 V is input to the gate of the switching device SWa and thereby the switching device SWa achieves an ON state, i.e., a conductive state. Therefore, the Low level signal (i.e., 0 V) input to the input terminal SIN is output to one of the input terminals of the NAND circuits 121 of the latch circuit 111 via the switching device SWa. By making the driving ability of the output circuit of the inverter 122 less than that of the output circuit of the first logic circuit 101, the voltage of the input terminal of the NAND circuit 121 can be decreased so as to be not greater than 1.0 V.
Therefore, the output terminal of the NAND circuit 121 achieves a High level of 3.0 V, and a Low level signal is output to the output terminal OUT by the inverter 123. In this case, a Low level signal is input to the input terminal of the NAND circuit 121, with which the switching device SWa is connected, by the inverter 122. In this state, the switching device SWa achieves a ON state, but a current is not flown to the first logic circuit 101 via the input terminal SIN because the voltages of the source and drain are both 0V.
When the fist voltage Vdd1 is not greater than the predetermined voltage a, a Low level signal SaB is output by the first control circuit 112 and in addition a Low level signal SbB is output by the latch control circuit 113. Thereby, the switching device SWa achieves an OFF state, i.e., a shut-off state. In addition, the output terminal of the NAND circuit 121 achieves a High level (i.e., 3.0 V) and a Low level signal is output to the output terminal OUT by the inverter 123.
However, the level shift circuit as illustrated in FIG. 3 can be used for only a case in which the first voltage Vdd1 applied to the first logic circuit 101 outputting a signal to the input terminal SIN is lower than the second voltage Vdd2 applied to the second logic circuit 102 to which a signal is to be input. Namely, the level shift circuit cannot be used for a case in which the first voltage Vdd1 is greater than the second voltage Vdd2.
Because of these reasons, a need exists for a level shift circuit which can be used for both the cases in which the first voltage Vdd1 is greater or less than the second voltage Vdd2.
Accordingly, an object of the present invention is to provide a level shift circuit which can be used for both of the case in which the first voltage Vdd1 applied to the first logic circuit, which outputs a signal, is smaller than the second voltage Vdd2 applied to the second logic circuit to which the signal is input; and the case in which the first voltage Vdd1 is greater than the second voltage Vdd2.
To achieve such objects, the present invention contemplates the provision of a level shift circuit, which performs level shift on a signal output from a first logic circuit operating on a first voltage to output the signal to a second logic circuit operated by a second voltage, including:
a switching circuit which is configured to perform input control of the signal output by the first logic circuit and which includes:
a first switching device; and
a second switching device, which is connected in series with the first switching device;
a first control circuit which operates on the first voltage and which is configured to control operation of the first switching device depending on the first voltage;
a second control circuit which operates on the second voltage and which is configured to control operation of the second switching device depending on the second voltage; and
a latch circuit which operates on the second voltage thereto and which is configured to perform level shift on amplitude of the signal output from the first logic circuit via the switching circuit so as to be the same as the second voltage and to latch a signal level of the level-shifted signal and output the signal to the second logic circuit,
wherein when the first voltage is not greater than a predetermined first voltage, the first control circuit allows the first switching device to turn off, and when the first voltage is greater than the predetermined first voltage, the first control circuit allows the first switching device to turn on, and wherein when the second voltage is not greater than a predetermined second voltage, the second control circuit allows the second switching device to turn off, and when the second voltage is greater than the predetermined second voltage, the second control circuit allows the second switching device to turn on.
Alternatively, the level shift circuit may be a level sift circuit, which performs level shift on a signal output from a first logic circuit operating on a first voltage to output the signal to a second logic circuit operated by a second voltage, including:
a switching circuit which is configured to perform input control of the signal output by the first logic circuit and which includes:
a first switching device; and
a second switching device, which is connected in series with the first switching device;
a first control circuit which operates on the first voltage and which is configured to control operation of the first switching device depending on the first voltage; and
a latch circuit which operates on the second voltage and which is configured to perform level shift on amplitude of the signal output from the first logic circuit via the switching circuit so as to be the same as the second voltage and to latch a signal level of the level-shifted signal and output the signal to the second logic circuit,
wherein when the first voltage is not greater than a predetermined first voltage, the first control circuit allows the first switching device to turn off, and when the first voltage is greater than the predetermined first voltage, the first control circuit allows the first switching device to turn on, and wherein the second switching device includes a MOS transistor, and the second voltage is applied to a gate of the MOS transistor.
In addition, the level shift circuit of the present invention may include a latch control circuit which operates on the second voltage and which is configured to control operation of the latch circuit depending on the first voltage. The latch control circuit outputs a predetermined signal to the latch control circuit when the first voltage is not greater than the predetermined first voltage.
Specifically, when the first voltage is greater than the predetermined first voltage, the latch control circuit performs level shift on the amplitude of the signal output from the first logic circuit via the switching circuit so as to be the same as that of the second voltage.
These and other objects, features and advantages of the present invention will become apparent upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.